Sr Principal Design Engineer
Cadence Pune
Job Description
Key Responsibilities- Own complete DFT implementation for assigned projects
- Define test architecture and identify required RTL modifications for DFT
- Perform scan insertion, low-power CLP checks, and logical equivalence checking (LEC)
- Develop timing constraints for test mode timing closure
- Perform scan and ATPG for various fault models
- Implement and verify boundary scan, ACJTAG, IEEE 1500, and IEEE 1687 (iJTAG) standards
- Run zero-delay and timing-aware simulations; debug issues across all DFT aspects
- Support post-silicon bring-up activities
- Collaborate with customers and support marketing & pre-sales teams on DFT solutions
- Work on high-speed and low-power design projects, ensuring test coverage and manufacturability
infospeed services, inc.Pune
Job Description
#Hiring#Pune#Automotive#Trims#Design
Let's #Join together for #WalkinDrive
Role- Automotive Interior Trim Design Engineer
Experience:- 2 to 10 Years
Location:- #Pune
Walk-in Interview- 6th & 7th June 2026 (Saturday & Sunday...
SiemensPune
and in the future. Does that sound like you Then it seems like you'd make an outstanding addition to our vibrant international team.
We are looking for a Design Engineer OHE/OCS/OLE – Contact Line Systems – Rail Electrification
You'll make a difference...
brose groupPune
in accordance with Product Workshops. Develop design concepts into qualitative cost-effective designs.
• Represents all design activities during product development, which calls for close co-operation with project engineers and test engineers. Interfaces...