Lead Design Engineer

apartmentCadence placePune calendar_month 

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • M.S. or BTech Electrical/Computer/Electronics Engineering (or similar degree)
  • Exp 4 - 8 years
  • Experience on cadence tools
  • Sound knowledge of PCIe and AMBA Protocols.
  • Hands on design/verification experience on AMBA based protocols like AXI, AHB, APB
  • Hands on experience in PCIe (GEN-5/6) /CXL (Compute Express Link) Controller Design, Functional Verification
  • Exposure to PCIe/UCIe/CXL Core Integration and Verification at SOC Level
  • Exposure to Controller and High Speed Serdes PIPE Interface
  • Exposure to Lint/CDC, Synthesis.
  • Exposure to all major IC implementation, design, and verification tools.
  • Strong debug and problem-solving skills
  • Ability to clearly communicate technical challenges.
  • Strong communications skills
  • Position Description (what the role does)
  • Technical interface for customer
  • Support customer Pre-post silicon SOC teams from initial PCIe Controller integration and bring-up.
  • Work closely with PCIe R&D team and Field Application Engineers
  • Update PCIe team with the latest customer feedback and competitive analysis.
  • Work closely with Physical design team and RTL team to understand chip architecture, hierarchy.
  • Perform RTL simulation to verify functionality.

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