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Synopsys Jobs

1 - 15 of 191
1 - 15 of 191
Search Results - Synopsys Jobs
Kandou AI-Hyderabad
using industry-standard EDA tools from Synopsys, Cadence, and Mentor/Siemens. 3 Proficient in scripting languages such as Tcl, Perl, or Python. 4 Experience with version control systems such as Git, SVN, etc. 5 Strong communication and presentation...
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1 similar jobs: Bangalore
Synopsys Inc-Gulbarga
Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market...
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6 similar jobs: Mysore, Belgaum, Bangalore, Vijāpura, Shimoga...
Sasken Technologies Limited-Sūrat
work at 7nm/5nm/3nm or below; FinFET closure mandatory, gate-all-around / advanced-node exposure a strong plus.  •  Tools: Strong hands-on with the Synopsys + Siemens flow used on this program:  •  Synthesis & PnR: Synopsys Fusion Compiler (or Design...
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6 similar jobs: Jamnagar, Ahmadābād, Rājkot, Jūnāgadh, Vadodara...
Sasken Technologies Limited-Vadodara
work at 7nm/5nm/3nm or below; FinFET closure mandatory, gate-all-around / advanced-node exposure a strong plus.  •  Tools: Strong hands-on with the Synopsys + Siemens flow used on this program:  •  Synthesis & PnR: Synopsys Fusion Compiler (or Design...
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6 similar jobs: Ahmadābād, Rājkot, Jamnagar, Jūnāgadh, Sūrat...
Sasken Technologies Limited-Rājkot
work at 7nm/5nm/3nm or below; FinFET closure mandatory, gate-all-around / advanced-node exposure a strong plus.  •  Tools: Strong hands-on with the Synopsys + Siemens flow used on this program:  •  Synthesis & PnR: Synopsys Fusion Compiler (or Design...
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jmmst.com -
ACL Digital-Bangalore
technologies.  •  Proficiency with Cadence Virtuoso, Mentor Graphics, Synopsys IC Compiler, or equivalent analog layout tools.  •  Hands-on experience with TSMC PDKs and process technologies for 7nm, 5nm, and 3nm nodes.  •  Strong knowledge of analog circuit design...
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Sasken Technologies Limited-Bhavnagar
work at 7nm/5nm/3nm or below; FinFET closure mandatory, gate-all-around / advanced-node exposure a strong plus.  •  Tools: Strong hands-on with the Synopsys + Siemens flow used on this program:  •  Synthesis & PnR: Synopsys Fusion Compiler (or Design...
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jmmst.com -
ACL Digital-Bangalore
in DFT for complex ASIC or SoC designs.  •  Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.  •  Hands-on experience with DFT tools such as:  •  Synopsys: DFT Compiler, TetraMAX, TestMAX  •  Siemens EDA: Tessent ScanPro, MBIST, IJTAG...
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Sasken Technologies Limited-Jamnagar
work at 7nm/5nm/3nm or below; FinFET closure mandatory, gate-all-around / advanced-node exposure a strong plus.  •  Tools: Strong hands-on with the Synopsys + Siemens flow used on this program:  •  Synthesis & PnR: Synopsys Fusion Compiler (or Design...
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jmmst.com -
leadIC Design Pvt Ltd-Bangalore
For  •  6+ years of hands-on STA experience  •  Strong expertise in Synopsys PrimeTime and/or Cadence Tempus  •  Excellent understanding of STA concepts and timing methodologies  •  Strong experience with SDC constraints  •  Good understanding of MCMM, OCV, AOCV...
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Mulya Technologies-Bangalore
focusing on designs at nodes ≤16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verificationflows...
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Mulya Technologies-Bangalore
and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ /n  •  16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon d /n  •  ebug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon...
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ACL Digital-Bangalore
knowledge of scan insertion, ATPG, MBIST, and boundary scan techniques.  •  Experience with industry tools such as:  •  DFT Tools: Synopsys DFT Compiler, Tetramax, TetraMAX II, Siemens Tessent  •  MBIST Tools: Synopsys TestMAX/DFTMAX, Tessent MBIST  •  Simulation...
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The Glove-Mysore
Models ✅ MBIST / LBIST ✅ JTAG / Boundary Scan – IEEE 1149.1 ✅ DFT Sign-off & Fault Coverage ✅ RTL & SoC Design Flow ✅ STA / Timing Closure ✅ DFT Debugging Tools & Scripting Siemens Tessent | Synopsys TestMAX | Cadence Modus | VCS TCL | Python | Perl...
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ACL Digital-Bangalore
with the ability to articulate complex technical challenges and solutions clearly to stakeholders. /n  •  Tool Flow Proficiency: Mastery over major industry-standard toolchains (Synopsys TestMax/DFTMAX/TetraMAX, Siemens Tessent suite, or Cadence Modus). /n  •  Genuine...
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